pl133- 27 low-power, 1. 62 v to 3.63v, 1mhz to 150mhz, 1:2 fanout buffer ic micrel inc. ? 2180 fortune drive ? san jose, ca 951 31 ? usa ? tel +1(408) 944 - 0800 ? fax +1(408) 474 - 1000 ? www.micrel.com rev 09 /13 /1 3 page 1 features ? 2 lvcmos outputs ? input/output frequency: 1mhz to 150mhz ? supports lvcmos or sine wave input clock ? extremely low additive jitter ? 8 ma o utput drive strength ? low current consumption ? single 1.8v, 2.5v, or 3.3v, 10% power supply ? operating temperature r ange o 0c to 70c (commercial) o - 40 ? c to 85 ? c (industrial) ? available in dfn-6l green/rohs compliant packages description the pl 133 - 27 is an advanced fanout buffer design for high performance, low-power, small form-factor applications. the pl133-27 accepts a reference clock input of 1mhz to 150mhz and produces two outputs of the same frequency. reference clock inputs may be lvcmos or sine-wave signals (the inputs are internally ac -coupled). pl133-27 is designed to fit in a small 2 x 1.3 x 0.6mm dfn pa ckage, and offers the best phase noise and jitter performance and lowest power consumption of any comparable ic. package pin configuration block diagram fin clk0 clk1 oe dfn-6l (2.0 x 1.3 x 0.6mm) fin gnd oe vdd clk0 clk1 1 4 5 6 3 2 downloaded from: http:///
pl133- 27 low-power, 1. 62 v to 3.63v, 1mhz to 150mhz, 1:2 fanout buffer ic micrel inc. ? 2180 fortune drive ? san jose, ca 951 31 ? usa ? tel +1(408) 944 - 0800 ? fax +1(408) 474 - 1000 ? www.micrel.com rev 09 /13 /1 3 page 2 package pin assignment name package pin # type description dfn- 6l fin 1 i reference clock input clk1 2 o clock output gnd 3 p gnd connection clk0 4 o clock o utput vdd 5 p v dd connection oe 6 i output enable input layout recommendations the following guidelines are to assist you with a p erformance optimized pcb design: signal integrity and termination considerations - keep traces short! - trace = inductor. with a capacitive load this eq uals ringing! - long trace = transmission line. without proper termination this will cause reflections (looks like ringing). - desi gn long traces as striplines or microstrips wit h defined impedance. - match trace at one side to avoid reflections boun cing back and forth. decoupling and power supply considerations - place decoupling capacitors as close as possible to the v dd pin(s) to limit noise from the power supply - multiple v dd pins should be decoupled separately for best performance. - addition of a ferrite bead in series with v dd can help prevent noise from other board sources - value of decoupling capacitor is frequency dependant. typical values to use are 0.1 ? f for designs using crystals < 50mhz and 0.01 ? f for designs using crystals > 50mhz. typical cmos termination place series resistor as close as possible to cmos output cmos output buffer (typical buffer impedance 20 ) to cmos input series resistor use value to match output buffer impedance to 50 trace. typical value 30 50 line downloaded from: http:///
pl133- 27 low-power, 1. 62 v to 3.63v, 1mhz to 150mhz, 1:2 fanout buffer ic micrel inc. ? 2180 fortune drive ? san jose, ca 951 31 ? usa ? tel +1(408) 944 - 0800 ? fax +1(408) 474 - 1000 ? www.micrel.com rev 09 /13 /1 3 page 3 electrical specifications absolute maximum ratings parameters symbol min. max. units supply voltage range v dd - 0.5 4.6 v input voltage range v i - 0.5 v dd +0.5 v output voltage range v o - 0.5 v dd +0.5 v storage temperature t s - 65 150 ? c ambient operating temperature* - 40 85 ? c exposure of the device under conditions beyond the limits specified by maximum ratings for extend ed periods may cause permanent damage to the device and affect product reliability. these conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. *operating temperature is guaranteed by design. parts are tested to commercial grade only. ac specifications parameters conditions min. typ. max. units input (fin) frequency @ v dd = 2.5v and 3.3v 1mhz 150 mhz @ v dd = 1.8v 65 in put (fin) signal amplitude internally ac coupled 0. 8 v dd v pp output rise time 15pf load, 1 0/ 90%v dd , 3.3v 2 3 ns output fall time 15pf load, 9 0/ 10%v dd , 3.3v 2 3 ns output to output skew 500 ps duty cycle input duty cycle is 50% 45 50 55 % dc specifications parameters symbol conditions min typ max units supply current, dynamic i dd v dd = 3.3v, 25mhz, no load 1.8 ma v dd = 2.5v, 25mhz, no load 1.3 ma v dd = 1.8v, 25mhz, no load 0. 8 ma operating voltage v dd 1.62 3.63 v output low voltage v ol i ol = +4ma , v dd = 3.3v 0.4 v output high voltage v oh i oh = -4ma , v dd = 3.3v 2.4 v output current i osd v ol = 0.4v, v oh = 2.4v, v dd = 3.3v 8 ma downloaded from: http:///
pl133- 27 low-power, 1. 62 v to 3.63v, 1mhz to 150mhz, 1:2 fanout buffer ic micrel inc. ? 2180 fortune drive ? san jose, ca 951 31 ? usa ? tel +1(408) 944 - 0800 ? fax +1(408) 474 - 1000 ? www.micrel.com rev 09 /13 /1 3 page 4 noise characteristics parameter symbol conditions min t yp m ax unit additive phase jitter v dd =3.3v, frequency=26mhz offset=12khz ~ 5mhz 130 fs v dd =3.3v, frequency=100mhz offset=12khz ~ 20mhz 15 0 fs pl133-27 additive phase jitter: vdd=3.3v, clk=26mhz, integration range 12khz to 5mhz: 0.127ps typical. -170 -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 10 100 1000 10000 100000 1000000 10000000 offset frequency (hz) phase noise (dbc/hz) ref input pl133-27 output when a buffer is used to pass a signal then the buffer will add a little bit of its own noise. the phase noise on the output of the buffer will be a little bit more than the phase noise in the input signal. to quantify the noise addition in the buffer we compare the phase jitter numbers from the input and the output. the difference is call ed "additive phase jitter". the formula for the additive phase jitter is as follows: additive phase jitter = (output phase jitter) - (input phase jitter) 2 2 downloaded from: http:///
pl133- 27 low-power, 1. 62 v to 3.63v, 1mhz to 150mhz, 1:2 fanout buffer ic micrel inc. ? 2180 fortune drive ? san jose, ca 951 31 ? usa ? tel +1(408) 944 - 0800 ? fax +1(408) 474 - 1000 ? www.micrel.com rev 09 /13 /1 3 page 5 d e pin 1 dot d1 b e e1 l a3 a a1 pin 6 id chamfer package drawings (green package compliant) dfn- 6l ordering information (green package) for part ordering, please contact our sales department: 21 80 fortune drive, san jose, ca 95131 , usa tel: (408) 944- 0800 fax: (408) 474 -1000 part number the order number for this device is a combination of the following: part number, package type and operating temperature range pl133-27 x x - r part number package type g=dfn-6l temperature range c=commercial (0c to 70c) i=industrial (-40c to 85c) r=tape and reel part/order number marking package option pl133- 27 gc-r h27 lll 6-pin dfn (tape and reel) pl133-27gi-r *note: l ll designates lot number micrel inc., reserves the right to make changes in its p roducts or specifications, or both at any time without no tice. the information furnished by micrel is believed to b e accurate and reliable. however, micrel makes no guarantee or wa rranty concerning the accuracy of said information and shall not be responsible for any loss or damage of wh atever nature resulting from the use of, or reliance upon th is product. life support policy : micrels products are not authorized for use as critic al components in life support devices or systems without the express w ritten approval of the president of micrel inc. symbol dimension in mm min. max. a 0. 45 0.60 a1 0.00 0.05 a3 0.152 0.152 b 0.15 0.25 e 0.40bsc d 1.25 1.35 e 1.95 2.05 d1 0.75 0.85 e1 0.95 1.05 l 0.20 0.30 downloaded from: http:///
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